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cy8cmbr2016 capsense ? express? 16 button matrix controller cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-67921 rev. *c revised october 31, 2012 capacitive button controllers features hardware configurable matrix capsense ? controller ? does not require software tools or programming ? 16 buttons can be configured individually or as a matrix ? supports 3x4 and 4x4 matrix configurations matrix host interface communication ? industry standard host interface protocols reuse existing host processor firmware ? key scan interface ? truth table interface ? encoded gpo interface - minimi zes number of pins required smartsense? auto-tuning ? maintains optimal button performance even in noisy environments ? capsense parameters dynamically set in runtime ? wide parasitic capacitance (c p ) range (5?40 pf) ? saves time and effort in device tuning noise immunity ? high sensitivity, low noise capacitive sensing algorithm ? strong immunity to rf and ac noise ? low radiated noise emission system diagnostics of capsense buttons ? reports any faults at device power up ? button shorts ? improper value of modulating capacitor (c mod ) ? parasitic capacitance (c p ) out of range advanced features ? flanking sensor suppression (fss) provides robust sensing even with closely spaced buttons ? buzzer signal output ? configurable sensitivity for all buttons ? interrupt line to host to indicate any capsense button status change ? serial debug data out ? simplifies production lin e testing and system debug wide operating range ? 1.71?5.5 v ? ideal for both regulated and unregulated battery applications [1] low power consumption ? supply current in run mode as low as 20 a [2] per button ? deep sleep current: 100 na industrial temperature range: ?40 c to + 85 c 48-pin qfn package (6 6 0.6 mm) overview the cy8cmbr2016 capsense express capacitive touch sensing controller incorporates several innovative features to save time and money to quickly enable a capacitive touch sensing user interface in your design. it is a hardware configurable device and does not require any software tools, firmware coding or device programming. this device is enabled with cypress's revolutionary smartsense ? auto-tuning algorithm. smartsense ? auto-tuning ends the need to manually tune the user interface during development and production ramp. this speeds the time to volume and saves valuable engineering time, test time and production yield loss. the device supports up to 16 capacitive touch buttons that can be organized in any format, such as a matrix array. with its backward compatible key scan interface, it can enable users to achieve quick-to-market (retrofit) designs in large keypad applications such as fire alarm control panels, security systems, and door locks. any app lication that requires up to 16 capsense buttons can utilize cy8cmbr2016. the wide operating range of 1.71 v to 5.5 v enables unregulated battery operation, further savi ng component cost. this device supports ultra low-power consumption in both run mode and deep sleep mode to stretch battery life. in addition, this device also supports many advanced features, which enhance the robustness and user interface of the end solution. some of the key advanced features include noise immunity and fss. noise immunity improves the immunity of the device against radiated and conducted noise, such as audio and radio frequency (rf) noise. fss provides robust sensing even with closely spaced buttons. fss is a critical requirement in small form factor applications. the cy8cmbr2016 provides three different host interface communication modes. these include the industry standard host interface protocols such as key scan interface and truth table interface. these two protocols reuse existing host processor firmware leading to easy conversion of existing mechanical buttons to capsense. the third host interface communication is the encoded gpo interface with a 4-bit output, which minimizes the number of pins required fo r a button output. these three outputs are configurable which helps provide a wide variety of device usage in multiple applications. serial debug data output gives t he critical information about the design, such as button cp and raw counts. this further helps in production line testing. notes 1. supply variation should not be more than 5% for proper capsense operation 2. power consumption calculated with 250 ms scan time, 2% touch time and c p of each button < 19 pf.
cy8cmbr2016 document number: 001-67921 rev. *c page 2 of 28 contents pinout ................................................................................ 3 typical circuits ................................................................. 4 configuring the cy8cmbr2016 . .............. .............. ......... 8 device features ................................................................ 8 capsense buttons ...................................................... 8 smartsense auto-tuning ............................................ 8 flanking sensor suppression (fss) ........................... 8 key scan interface ...................................................... 8 truth table output .................................................... 10 encoded 4-bit output ................................................ 10 buzzer signal output ................................................ 10 interrupt line ............................................................. 10 button auto reset ............... ...................................... 10 output select ............................................................. 11 scan rate .................................................................. 11 sensitivity .................................................................. 11 system diagnostics ................................................... 11 serial debug data out .............................................. 12 power consumption and device operating modes .. 15 response time ........ .............. .............. .............. ....... 15 deep sleep mode ...... .............. ............... ........... ........ 16 layout guidelines and best practices ......................... 16 sample layout ................................................................ 19 electrical specifications ................................................ 21 dc electrical characteristics ..................................... 21 ac electrical specifications ....................................... 23 capsense specification ............................................ 23 package information ...................................................... 24 ordering information ...................................................... 25 ordering code definitions ..... .................................... 25 appendix ......................................................................... 26 acronyms ........................................................................ 27 document conventions ................................................. 27 units of measure ....................................................... 27 document history page ................................................. 28 sales, solutions, and legal information ...................... 28 worldwide sales and design s upport ......... .............. 28 products .................................................................... 28 psoc solutions ................................................................ 28
cy8cmbr2016 document number: 001-67921 rev. *c page 3 of 28 pinout table 1. pinout for the device pin pin name type description figure 1. device pinout 1 nc ? no connection 2 out_7 do read_3/tt_row_3/eo_3/ fmea_clk line - output port interface pin 7 3 out_5 do read_1/tt_row_1/eo_1 - output port interface pin 5 4 out_3 dio scan_3/tt_col_3 - output port interface pin 3 5 out_1 dio scan_1/tt_col_1 - output port interface pin 1 6 out_sel ai selects the output interface 7 arst ai controls button auto reset period 8 cs9 ai capsense button 9 9 cs8 ai capsense button 8 10 cs13 ai capsense button 13 11 cs12 ai capsense button 12 12 nc ? reserved pin 13 fss di controls fss feature 14 nc ? no connection 15 nc ? no connection 16 sleep di controls entry/exit to deep sleep 17 debug do serial debug data out from the device (uart tx8 line) 18 v ss ?gnd 19 nc ? no connection 34 out_2 dio scan_2/tt_col_2 - output port interface pin 2 20 nc ? no connection 35 out_4 do read_0/tt_row_0/eo_0 - output port interface pin 4 21 v dd ? power supply 36 out_6 do read_0/tt_row_0/eo_2/fmea_d ata - output port interface pin 6 22 sensitivity ai selects the sensitivity of the cs system 37 cs3 ai capsense button 3 23 nc ? reserved for shield out 38 cs2 ai capsense button 2 24 buzzer do connects to dc buzzer for audio feedback 39 cs1 ai capsense button 1 25 scan ai controls the sleep rate of the system 40 cs0 ai capsense button 0 26 xres di system reset pin 41 vdd ? power supply 27 cs15 ai capsense button 15 42 nc ? no connection 28 cs14 ai capsense button 14 43 nc ? no connection 29 cs11 ai capsense button 11 44 cs5 ai capsense button 5 30 cs10 ai capsense button 10 45 cs4 ai capsense button 4 31 cs7 ai capsense button 7 46 int do interrupt line to host 32 cs6 ai capsense button 6 47 vss ? gnd 33 out_0 dio scan_0/tt_col_0 - output port interface pin 0 48 c mod ai modulator capacitor, 2.2 nf cy8cmbr2016 vss vdd nc 35 34 33 32 36 48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 nc nc (top view) 10 11 12 31 30 29 28 27 26 25 xres 6 7 8 9 13 14 15 16 17 18 19 20 21 22 23 24 n c v s s vdd nc cs12 cs13 cs8 cs9 arst out_sel c n nc debug out_7 cmod cs4 cs5 cs3 cs0 cs1 sleep buzzer scan cs15 cs14 cs11 cs10 cs7 cs6 cs2 fss n c sensitivity nc int out_5 out_3 out_1 out_6 out_4 out_2 out_0
cy8cmbr2016 document number: 001-67921 rev. *c page 4 of 28 typical circuits figure 2. schematic 1: 16 buttons with key scan output mode host hdr read_0 read_1 read_2 read_3 scan_0 scan_1 scan_2 scan_3 int line x host scan lines read lines scan lines (odl mode) read lines (strong drive) mechanical keypad int
cy8cmbr2016 document number: 001-67921 rev. *c page 5 of 28 in schematic 1, cy8cmbr2016 is configured as follows: 16 capsense buttons key scan interface continuous scan mode high sensitivity for all buttons fss enabled button auto reset disabled serial debug data out disabled dc buzzer output reset button interrupt line output
cy8cmbr2016 document number: 001-67921 rev. *c page 6 of 28 figure 3. schematic 2: 16 buttons with truth table output mode
cy8cmbr2016 document number: 001-67921 rev. *c page 7 of 28 in schematic 2, cy8cmbr2016 is configured as follows: 16 capsense buttons truth table output configured to drive leds continuous scan mode high sensitivity for all buttons fss disabled button auto reset enable, with a period of 5 seconds serial debug data out enabled dc buzzer output reset button interrupt line output
cy8cmbr2016 document number: 001-67921 rev. *c page 8 of 28 configuring th e cy8cmbr2016 the cy8cmbr2016 device feat ures are configured using external resistors. the resistors on the hardware configurable pins are determined by the device upon power-on. the appendix on page 26 gives the matrix of features enabled using different external resistor configurations. device features capsense buttons device supports up to 16 capsense buttons. ground the csx pin to disable capsense input. 2.2 nf ( 10%) capacitor should be connected on c mod pin for proper capsense operation. the parasitic capacitance (c p ) of each button must be less than 40 pf for proper capsense operation. smartsense auto-tuning device supports auto-tuning of capsense button parameters. no manual tuning required; all parameters are automatically tuned by the device. compensates printed circuit board (pcb) variations, device process variations, and pcb vendor changes. ensures portability of the user interface design. flanking sensor suppression (fss) helps to distinguish closely spaced buttons. also used in situations when a button can produce opposite effects. for example, an interface with two buttons for brightness control (up or down). fss action can be explained for the following different scenarios: ? when only one button is touc hed, it is reported as on. ? when more than one button is det ected as on and previously one of those buttons was touc hed, then the previously touched button is report ed as on. (refer to figure 4 .) key scan interface mimics legacy mechanical keypads - four scan lines (i/p) and four read lines (o/p) reads the scan lines and updates the read lines based on the button status (refer to figure 5 ). ?plug' n 'play' replacement for mechanical keypads. when buttons are disabled or found to be invalid, ta b l e 3 helps identifying the scan and read lines. when the scan lines are not used, they should be connected to v dd out0 to out3 in the pin out form the scan lines and out4 to out7 form the read lines refer figure 6 for scan line waveform details. table 2. device feature list feature description/use 16 capsense buttons mechanical button/keypad replacement flanking sensor suppression (fss) helps in distinguishing closely spaced buttons key scan interface mechanical matrix replacement truth table output easy to decode truth table based output mode 4-bit encoded output fewer pins needed to output button status button auto reset prevents buttons from getting stuck during run time scan/sleep rate configures the device based on power needs configurable sensi- tivity selects the sensitivity for the system ? minimum change in capacitance to be detected deep sleep reduce power consumption by hibernating the device system diagnostics supports for production testing and debugging table 3. key scan interface selection based on # of buttons no. of buttons scan read lines scan lines (>12) 4 4 out0 to out3 (<=12) && (>8) 3 4 out0 to out2 (<=8) && (>4) 2 4 out0 to out1 (<=4) 1 4 out0
cy8cmbr2016 document number: 001-67921 rev. *c page 9 of 28 figure 4. button status with respect to finger touch when fss is enabled [3] note 3. when finger moves from one button to other (fss enabled). x host scan lines read lines cy8cmbr2016 scan lines (odl mode) read lines (strong drive) mechanical keypad figure 5. key scan interface retrofit figure 6. scan line waveform details
cy8cmbr2016 document number: 001-67921 rev. *c page 10 of 28 truth table output another output interface pr oviding matrix outputs. all pins are output pins - divided into row/column. only one button can be reported at a time - cannot be used in conjunction with fss disabled. button status is reported in an encoded row/column fashion as shown in figure 7 . each button has its own row-column code. easy to integrate into a system r equiring a simple interface with single key press requirement. out4 to out7 in the pin out form the row lines and out0 to out3 form the column lines. encoded 4-bit output only 4 pins to report a button press out of 16 buttons. each button has its own code. only one button can be reported at a time using this interface. table 4 defines the decode table. buzzer signal output a dedicated pin for buzzer output is provided in the device. buzzer output can be used to drive an p-type transistor driving a buzzer or directly a dc buzzer up to 10 ma sink current. interrupt line an interrupt line to the host controller. on a button touch, the device pulls the int line high to indicate an interrupt to the host. the int line remains high as long as a button is touched. can be used as a latch input at the host side to read the out lines. can also be used as an interrupt line for the host controller to read the out lines. button auto reset prevents button stuck, due to any conducting object placed close to a button. useful when output to be kept on only for a specific time. the button auto reset period is controlled by the hardware configuration on the arst pin. refer table 18 in appendix on page 26 for pin configuration details. when touched, a button is treated active for a maximum of button auto reset period (refer to figure 8 ). after the button is released the csx will be hold for 440 ms. figure 7. truth table output table 4. encoded output keypress detected by capsense eo[3:0] interrupt time key #1 0000 1 key #2 0001 1 key #3 0010 1 key #4 0011 1 ??1 key #16 1111 1 no keys pressed xxxx 0
cy8cmbr2016 document number: 001-67921 rev. *c page 11 of 28 output select one among the three output interf aces defined earlier in the section can be selected by the hardware configuration on the out_sel pin. refer ta b l e 1 8 in appendix on page 26 for pin configuration details. only one of the three output inte rfaces can be used at a given time. scan rate this defines the rate at which the device scans all the buttons and then sleeps, in the low power sleep mode. for more details about low power sleep mode, refer to power consumption and device operating modes on page 15 . the device scan rate is defined by the hardware configuration on the scan pin. refer ta b l e 1 8 in appendix on page 26 for details. device power consumption is dependent on scan rate. for a higher scan rate, the power consumption is less, and vice versa. refer to the cy8cmbr2016 design guide , section 5 for power calculations. sensitivity sensitivity is defined as the minimum change in capacitance which can be detected as a finger touch. use higher sensitivit y setting when the overlay thickness is higher, or the button diameter is small. use a lower sensitivity setting when power consumption needs to be low. possible sensitivity settings are ?high?, ?medium?, and ?low?. sensitivity can be controlled by the hardware configuration on the sensitivity pin. for details, refer to table 18 in appendix on page 26 . system diagnostics a built-in power on self test (post) mechanism detects the following at power on reset (por), which can be useful in production testing. any failure is reported on the out_6 and out_7 pins, as detailed below. button shorted to ground if a button is disabled/found shorted to ground (as shown in figure 11 ), then the corresponding bit in the button mask is set, and the same is sent out serially through the out_6 pin, synchronised with a 2 khz clock on out_7 pin. if no clock is sensed on out_7 till 300 ms after power-on, then all the buttons have passed the system diagnostics. if a clock is sensed, then starting from the first falling edge of the clock, each button takes up one clock slot. a high output on out_6 during a falling edge on out_7 indicates a failure of the button in that clock slot. the clock output stops after indicating the last failed button. for instance, if button 1, 3 and 5 are disabled, then the system diagnostics data is transmitted as shown in figure 9 . cs1 failure is marked by a high on out_6 in the 0.5 ms to 1 ms slot. cs3 failure is marked by a high on out_ 6 in the 1.5 ms to 2 ms slot. cs5 failure is marked by a high on out_6 in the 2.5 ms to 3 ms slot. after indicating the failure of cs5, clock output is ceased. as an example, figure 10 shows the system diagnostics output when cs1, cs3 and cs15 fail the post. figure 8. button auto reset button output auto ? reset ? period output ? is ? not ? driven ? after ? auto ? reset ? period button ? is ? touched ? for ? more ? than ? the ? auto ? reset ? period figure 9. system diagnostics of disabled button - scenario 1
cy8cmbr2016 document number: 001-67921 rev. *c page 12 of 28 button shorted to v dd if any button is shorted to v dd that button is disabled and the corresponding bit field is set and system diagnostics data is sent as defined in button to gnd short section. button to button short any button that are shorted t ogether are disabled and the corresponding bit field is set and system diagnostics data is sent as defined in button to gnd short section. improper value of c mod recommended value of c mod is 2 nf to 2.4 nf. if c mod of < 1 nf or > 4 nf is co nnected, all buttons are disabled and the status output will be logic high on all slots. button c p > 40 pf if the parasitic capacitance (c p ) of any button exceeds 40 pf that button is disabled and the corresponding bit field is set and system diagnostics data is sent as defined in button to gnd short section. serial debug data out used to see capsense data through the debug pin. to enable this feature, the debug pin is pulled down with a 5.6 k resistor. the cypress multichart tool can be used to view the debug data for each button serial data is sent out at ~115,200 baud rate firmware revision, capsense status, baseline, raw counts, difference counts and parasitic capacitances of all sensors are sent out for more information on raw count, baseline, difference count, and parasitic capacitance, refer getting started with capsense , section 2. figure 10. system diagnostics of disabled button - scenario 2 figure 11. button shorted to gnd cy8cmbr2016 button shorting figure 12. butto n shorted to v dd cy8cmbr2016 button shorting v dd figure 13. button to button short cy8cmbr2016 button shorting button
cy8cmbr2016 document number: 001-67921 rev. *c page 13 of 28 for more information on multichart tool, refer an2397 - capsense data viewing tools , method 2. the multichart tool arranges the data in the format as shown in table 5 on page 13 . the serial debug data is sent by the device in the order shown in table 6 on page 13 . table 5. serial debug data arranged in multichart sl. no. raw count array baseline array difference count array msb lsb msb lsb msb lsb 0 cs0_rc cs0_bl cs0_diff 1 cs1_rc cs1_bl cs1_diff 2 cs2_rc cs2_bl cs2_diff 3 cs3_rc cs3_bl cs3_diff 4 cs4_rc cs4_bl cs4_diff 5 cs5_rc cs5_bl cs5_diff 6 cs6_rc cs6_bl cs6_diff 7 cs7_rc cs7_bl cs7_diff 8 cs8_rc cs8_bl cs8_diff 9 cs9_rc cs9_bl cs9_diff 10 cs10_rc cs10_bl cs10_diff 11 cs11_rc cs11_bl cs11_diff 12 cs12_rc cs12_bl cs12_diff 13 cs13_rc cs13_bl cs13_diff 14 cs14_rc cs14_bl cs14_diff 15 cs15_rc cs15_bl cs15_diff 16 0x00 f/w rev cs_status 0x00 cs10_cp 17 0x00 cs0_cp 0x00 cs5_cp 0x00 cs11_cp 18 0x00 cs1_cp 0x00 cs6_cp 0x00 cs12_cp 19 0x00 cs2_cp 0x00 cs7_cp 0x00 cs13_cp 20 0x00 cs3_cp 0x00 cs8_cp 0x00 cs14_cp 21 0x00 cs4_cp 0x00 cs9_cp 0x00 cs15_cp table 6. serial data output sent by cy8cmbr2016 byte data notes 0 0x0d dummy variables for multi chart tool 1 0x0a 2 cs0_rc cs0 raw counts, unsigned 16-bit integer 3 4 cs1_rc cs1 raw counts, unsigned 16-bit integer 5 6 cs2_rc cs2 raw counts, unsigned 16-bit integer 7 ----- ------------ ------------------------------------------------------
cy8cmbr2016 document number: 001-67921 rev. *c page 14 of 28 32 cs15_rc cs15 raw counts, unsigned 16-bit integer 33 34 0x00 ? 35 fw_rev firmware revision 36 0x00 ? 37 cs0_cp parasitic capacitance of cs0 38 0x00 ? 39 cs1_cp parasitic capacitance of cs1 40 0x00 ? 41 cs2_cp parasitic capacitance of cs2 42 0x00 ? 43 cs3_cp parasitic capacitance of cs3 44 0x00 ? 45 cs4_cp parasitic capacitance of cs4 46 cs0_bl cs0 baseline, unsigned 16-bit integer 47 48 cs1_bl cs1 baseline, unsigned 16-bit integer 49 50 cs2_bl cs2 baseline, unsigned 16-bit integer 51 ------------ ------------------------------------------------------ 76 cs15_bl cs15 baseline, unsigned 16-bit integer 77 78 79 cs_status capsense status, unsigned 16 bit integer ? 80 0x00 ? 81 cs5_cp parasitic capacitance of cs5 82 0x00 ? 83 cs6_cp parasitic capacitance of cs6 84 0x00 ? 85 cs7_cp parasitic capacitance of cs7 86 0x00 ? 87 cs8_cp parasitic capacitance of cs8 88 0x00 ? 89 cs9_cp parasitic capacitance of cs9 90 cs0_diff cs0 difference counts, unsigned 16-bit integer 91 92 cs1_ diff cs1 difference counts, unsigned 16-bit integer 93 94 cs2_ diff cs2 difference counts, unsigned 16-bit integer ------------ ------------------------------------------------------ table 6. serial data output sent by cy8cmbr2016 (continued) byte data notes
cy8cmbr2016 document number: 001-67921 rev. *c page 15 of 28 power consumption and device operating modes the cy8cmbr2016 is designed to meet the low power requirements of battery powered applications. to design for the lowest operating current - ground all unused capsense inputs minimize cp using the design guidelines in getting started with capsense , section 3.7.1. lower the supply voltage. use a higher button scan rate or deep sleep operating mode. to know more about the steps to reduce power consumption, refer to cy8cmbr2016 design guide , section 5. there are two device operating modes: low power sleep mode deep sleep mode low power sleep mode the following flow chart describes the low power sleep mode operation. figure 14. low power sleep mode operation for details on low power sleep look at the scan rate on page 11 section. response time response time is the minimum amount of time the button should be touched for the device to detect as valid button touch. it is given by the following equations - rt fbt =user defined button scan rate + 40 ms rt cbt = 40 ms where, rt fbt is response time for first button touch rt cbt is response time for consecutive button touch after first button touch 121 cs15_ diff cs15 difference counts, unsigned 16-bit integer 122 123 0x00 ? 124 cs10_cp parasitic capacitance of cs10 125 0x00 ? 126 cs11_cp parasitic capacitance of cs11 127 0x00 ? 128 cs12_cp parasitic capacitance of cs12 129 0x00 ? 130 cs13_cp parasitic capacitance of cs13 131 0x00 ? 132 cs14_cp parasitic capacitance of cs14 133 0x00 ? 134 cs15_cp parasitic capacitance of cs15 135 0x00 dummy variable for multi chart tool 136 0xff 137 0xff table 6. serial data output sent by cy8cmbr2016 (continued) byte data notes
cy8cmbr2016 document number: 001-67921 rev. *c page 16 of 28 refer to scan rate on page 11 section for more details on the user defined button scan rate. for example, consider a nine bu tton design with the user defined button scan rate set to low (250 ms). the response time for such a design is given as: rt fbt =250+40=290 ms rt cbt = 40 ms deep sleep mode figure 15. sleep pin configuration to enable deep sleep to enable the deep sleep mode, the hardware configuration pin sleep should be connected to the master device. master should pull the pin to v dd for the device to go into deep sleep. the master output pin should be in strong drive mode, so that the sleep pin is not left floating. in deep sleep mode, all blocks are turned off and the device power consumption is 0.1 a. there is no capsense scanning in deep sleep mode. sleep pin should be pulled low for the device to wake up from deep sleep. when device comes out of deep sleep mode, the capsense system is reinitialized. typical time for re-initialization is 8 ms.any button press within this time is not reported. after the device comes out of deep sleep, the device operates in low power sleep mode. if the sleep pin is pulled high at power on, then the device does not go to deep sleep immediately. the device goes to deep sleep after initializ ing all internal bl ocks and scanning all sensors once. if the sleep pin is pulled high at power on, then the scan rate is calculated when the device is taken out of deep sleep by the master. layout guidelines and best practices cy8cmbr2016 host controller sleep digital output pin (controls deep sleep) table 7. layout guidelines sl. no. category min max recommendations/remarks 1. button shape ?? solid round pattern, round with led hole, rectangle with round corners 2. button size 5 mm 15 mm given in layout estimator sheet 3. button-button spacing equal to button ground clearance 8 mm 4. button ground clearance 0.5 mm 2 mm given in layout estimator sheet 5. ground flood - top layer ?? hatched ground 7 mil trace and 45 mil grid (15% filling) 6. ground flood - bottom layer ?? hatched ground 7 mil trace and 70 mil grid (10% filling) 7. trace length from sensor to device pin ? 450 given in layout estimator sheet 8. trace width 0.17 mm 0.20 mm 0.17 mm (7 mil) 9. trace routing ?? traces should be routed on the non sensor side. if any non capsense trace crosses capsense trace, ensure that intersection is orthogonal. 10. via position for the sensors ?? via should be placed near the edge of the button to reduce trace length thereby increasing sensitivity. 11. via hole size for sensor traces ?? 10 mil 12. no. of via on sensor trace 1 2 1
cy8cmbr2016 document number: 001-67921 rev. *c page 17 of 28 figure 16. capsense button shapes figure 17. button layout design x: button to ground clearance (refer to layout guidelines and best practices on page 16 ) 13. capsense series resistor placement ? 10 mm place capsense series resistors close to the device for noise suppression.capsense resistors have highest priority compared to other resistors, so place them first. 14. distance between any capsense trace to ground flood 10 mil 20 mil 20 mil 15. device placement ?? mount the device on the layer opposite to sensor. the capsense trace length between the device and sensors should be minimum (see trace length above) 16. placement of components in two layer pcb ?? top layer-sensors and bottom layer-device, other components and traces. 17. placement of components in four layer pcb ?? top layer-sensors, second layer ? capsense traces & vdd and avoid the vdd traces below the sensors, third layer-hatched ground, bottom layer- device other components and non capsense traces 18. overlay thickness 0 mm 5 mm use layout estimator sheet to decide on overlay, given maximum limit is for plastic overlay. 19. overlay material ?? should to be non-conductive material. glass, abs plastic, formica, wood etc. no air gap should be t here between pcb and overlay. use adhesive to stick the pcb and overlay. 20. overlay adhesives ?? adhesive should be non conductive and dielectrically homogenous. 467 mp and 468 mp adhesives made by 3 m are recommended. 21. board thickness ?? standard board thickness for capsense fr4 based designs is 1.6 mm. table 7. layout guidelines (continued) sl. no. category min max recommendations/remarks
cy8cmbr2016 document number: 001-67921 rev. *c page 18 of 28 y: button to button clearance (refer to layout guidelines and best practices on page 16 ) figure 18. recommended via hole placement
cy8cmbr2016 document number: 001-67921 rev. *c page 19 of 28 sample layout figure 19. top layer
cy8cmbr2016 document number: 001-67921 rev. *c page 20 of 28 figure 20. bottom layer
cy8cmbr2016 document number: 001-67921 rev. *c page 21 of 28 electrical specifications this section presents the dc and ac electric al specifications of the cy8cmbr2044 device. table 8. absolute maximum ratings parameter description min typ max unit notes t stg storage temperature ?55 25 +125 c higher storage temperatures reduce data retention time. recommended storage temperature is +25 c 25 c. extended duration storage temperatures above 85 c degrade reliability. v dd supply voltage relative to v ss ?0.5 ? +6.0 v ? v io dc voltage on capsense inputs and digital output pins v ss ? 0.5 ? v dd + 0.5 v ? i mig maximum current into any gpo output pin ?25 ? +50 ma ? esd electrostatic discharge voltage 2000 ? ? v human body model esd lu latch up current ? ? 200 ma in accordance with jesd78 standard table 9. operating temperature parameter description min typ max unit notes t a ambient temperature ?40 ? +85 c ? t c commercial temperature 0 ? +70 c ? t j operational die temperature ?40 ? +100 c ? dc electrical characteristics the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 10. dc chip level specifications parameter description min typ max unit notes v dd [4, 5, 6] supply voltage 1.71 ? 5.5 v ? i dd supply current ? 3.3 4.0 ma conditions are v dd = 3.0 v, t a = 25 c i da active current ? 3.3 4.0 ma conditions are v dd = 3.0 v, t a = 25 c, continuous sensor scan i ds deep sleep current ? 0.1 0.5 ? a conditions are v dd = 3.0 v, t a = 25 c i av1 average current ? 0.25 ? ma conditions are v dd = 3.0 v, t a = 25 c and 16 buttons used, with 0% touch time, c p of all sensors < 19 pfand scan rate = 250 ms i av2 average current ? 2.13 ? ma conditions are v dd = 3.0 v, t a = 25 c and 16 buttons used, with 50% touch time, c p of all sensors < 19 pfand scan rate = 250 ms, key scan mode enabled i av3 average current ? 0.42 ? ma conditions are v dd = 3.0 v, t a = 25 c and 16 buttons used, with 0% touch time, c p of all sensors >19 pf and < 40 pf and scan rate = 250 ms i av4 average current ? 2.2 ? ma conditions are v dd = 3.0 v, t a = 25 c and 16 buttons used, with 50% touch time, c p of all sensors >19 pf and < 40 pf and scan rate = 250 ms, key scan mode enabled notes 4. when v dd remains in the range from 1.75 v to 1.9 v for more than 50 s, the slew rate when moving from the 1.75 v to 1.9 v range to gre ater than 2 v must be slower than 1 v/500 s. this helps to avoid triggering por. the only other restriction on slew rates for any other voltage rang e or transition is the sr power_up parameter. 5. after power down, ensure that v dd falls below 100 mv before powering backup. 6. for proper capsense block functionality, if the drop in v dd exceeds 5% of the base v dd , the rate at which v dd drops should not exceed 200 mv/s. base v dd can be between 1.8 v and 5.5 v
cy8cmbr2016 document number: 001-67921 rev. *c page 22 of 28 dc general purpose i/o specifications these tables list guaranteed maximum and minimum specifications for the voltage and temperature ranges: 3.0 v to 5.5 v and ?40 c ? t a ? 85 c, 2.4 v to 3.0 v and ?40 c ? t a ? 85 c, or 1.71 v to 2.4 v and ?40 c ? t a ? 85 c, respectively. typical parameters apply to 5 v and 3.3 v at 25 c and are for design guidance only. table 11. 3.0 v to 5.5 v dc general purpose i/o specification parameter description min typ max unit notes v oh1 high output voltage on all output pins v dd ? 0.2 ? ? v i oh < 10 a, maximum of 40 a source in all i/os v oh2 high output voltage on out pins v dd ? 0.9 ? ? v i oh = 1 ma, maximum of 2 ma source in all i/os v oh3 high output voltage on int and buzz pins v dd ? 0.9 ? ? v i oh = 5 ma, maximum of 10 ma source in all i/os v ol low output voltage ? ? 0.75 v i ol = 25 ma/pin, v dd > 3.3 v, maximum of 60 ma source in all i/os v il input low voltage ? ? 0.80 v ? v ih input high voltage 2.00 ? ? v ? table 12. 2.4 v to 3.0 v dc general purpose i/o specifications parameter description min typ max unit notes v oh1 high output voltage on all outputs v dd ? 0.2 ? ? v i oh < 10 a, maximum of 40 a source in all i/os v oh2 high output voltage on out pins v dd ? 0.4 ? ? v i oh = 0.2 ma, maximum of 0.4 ma source in all i/os v oh3 high output voltage on int and buzz v dd ? 0.5 ? ? v i oh = 2 ma, maximum of 4 ma source in all i/os v ol low output voltage ? ? 0.75 v i ol = 10 ma/pin, v dd > 3.3 v, maximum of 30 ma source in all i/os v il input low voltage ? ? 0.72 v ? v ih input high voltage 1.40 ? ? v ? table 13. 1.71 v to 2.4 v dc general purpose i/o specifications parameter description min typ max unit notes v oh1 high output voltage on out pins v dd ? 0.2 ? ? v i oh =10 a, maximum of 20 a source in all i/os v oh2 high output voltage on out pins v dd ? 0.5 ? ? v i oh = 0.5 ma, maximum of 1 ma source in all i/os v oh3 high output voltage on int and buzz v dd ? 0.2 ? ? v i oh =100 a, maximum of 200 a source in all i/os v oh4 high output voltage on int and buzz v dd ? 0.5 ? ? v i oh = 2 ma, maximum of 4 ma source in all i/os v ol low output voltage ? ? 0.4 v i ol = 5 ma/pin, v dd > 3.3 v, maximum of 20 ma source in all i/os v il input low voltage ? ? 0.30 v dd v? v ih input high voltage 0.65 v dd ??v?
cy8cmbr2016 document number: 001-67921 rev. *c page 23 of 28 ac electrical specifications the following table lists guaranteed maximum and minimum spec ifications for the entire voltage and temperature ranges. table 14. ac chip-level specifications parameter description min max unit notes sr power_up power supply slew rate ? 250 v/ms v dd slew rate during power-up t xrst external reset pulse width at power-up 1 ? ms applicable after device power supply is active t xrst2 external reset pulse width after power-up 10 ? ms applicable after device v dd has reached maximum value table 15. ac general purpose i/o specifications parameter description min typ max unit notes t rise1 rise time on out pins, cload = 50 pf 15 ? 80 ns v dd = 3.0 to 3.6 v, 10%?90% t rise2 rise time on int and buzz pins, cload = 50 pf 10 ? 50 ns v dd = 3.0 to 3.6 v, 10%?90% t rise3 rise time on out pins, cload = 50 pf 15 ? 80 ns v dd = 1.71 to 3.0 v, 10%?90% t rise4 rise time on int and buzz pins, cload = 50 pf 10 ? 80 ns v dd = 1.71 to 3.0 v, 10%?90% t fall1 fall time, cload = 50 pf all outputs 10 ? 50 ns v dd = 3.0 to 3.6 v, 90%?10% t fall2 fall time, cload = 50 pf all outputs 10 ? 70 ns v dd = 1.71 to 3.0 v, 90%?10% capsense specification parameter description min typ max unit notes c p parasitic capacitance 5.0 ? (c p +c f )<40 pf c p is the total capacitance seen by the pin when no finger is present. c p is sum of c_sensor, c_trace, and capacitance of the vias and c pin c f finger capacitance 0.25 ? (c p +c f )<40 pf c f is the capacitance added by the finger touch c pin capacitive load on pins as input 0.5 1.7 7 pf mandatory for capsense to work c mod external modulator capacitor 2 2.2 2.4 nf mandatory for capsense to work r s series resistor between pin and the button ? 560 616 ? reduces the rf noise
cy8cmbr2016 document number: 001-67921 rev. *c page 24 of 28 package information table 16. thermal impedances by package table 17. solder reflow peak temperature figure 21. 48-pin (6 6 0.6 mm) qfn package typical ja [7] 48-pin qfn [8] 19 c/w package minimum peak temperature [9] maximum peak temperature time at max temperature 48-pin qfn 240 c 260 c 30 s 001-57280 *d notes 7. t j = t a + power x ja 8. to achieve the thermal impedance specified for the qfn package, the center thermal pad must be soldered to the pcb ground pla ne 9. higher temperatures may be required based on the solder melting point. typical temperatures for solder are 220 5 c with sn -pb or 245 5 c with sn-ag-cu paste. refer to the solder manufacturer specifications
cy8cmbr2016 document number: 001-67921 rev. *c page 25 of 28 ordering information ordering code package type operating temperature capsense inputs other i/os xres pin cy8cmbr2016-24lqxi 48-pin (6 6 0.6 mm) qfn industrial 17 [10] 17 [11] yes CY8CMBR2016-24LQXIT 48-pin (6 6 0.6 mm) qfn (tape and reel) industrial 17 [10] 17 [11] yes ordering code definitions t = tape and reel, blank = standard temperature range: i = industrial package code: lqx = qfn pb-free speed: 24 mhz part number: 2016 mbr = mechanical button replacement technology code: c = cmos marketing code: 8 = psoc company id: cy = cypress 8 cy c mbr 2016 24 lqx (t) i - notes 10. 16 capsense input + 1 c mod pin 11. 8 configurable gpios + 1 buzzer output + 1 sleep line + 1 interrupt line + 1 debug line + 5 configuration pins
cy8cmbr2016 document number: 001-67921 rev. *c page 26 of 28 appendix table 18. device features versus resistor configuration matrix features comments pin configuration device pin name flanking sensor suppression (fss) disabled ground fss enabled vdd / floating button auto reset enabled, auto reset period = 5 ms ground arst enabled, auto reset period = 20 ms 1.5 k ? (5%) to ground enabled, auto reset period = 40 ms 5 k ? (5%) to ground disabled vdd / floating output select truth table i/f ground out_sel encoded 4 bit output 1.5 k ? (5%) to ground keypad scanning interface output vdd / floating scan rate low, 250 ms ground scan medium, 150 ms 1.5 k ? (5%) to ground high, 40 ms 5 k ? (5%) to ground continuous scan vdd / floating sensitivity low ground sensitivity medium 1.5 k ? (5%) to ground high vdd / floating deep sleep mode device out of deep sleep ground sleep device in deep sleep vdd
cy8cmbr2016 document number: 001-67921 rev. *c page 27 of 28 acronyms document conventions units of measure acronym description ac alternating current c f finger capacitance c mod modulator capacitor c p parasitic capacitance eo_x encoded output - bit ?x? fmea failure mode effect analysis fss flanking sensor suppression odl open drain low por power-on reset post power on self test qfn quad flat no leads rf radio frequency read_x keyscan interface - ?x?th read line scan_x keyscan interface - ?x?th scan line snr signal-to-noise ratio tt_col_x truth table column output - ?x?th column tt_row_x truth table row output - ?x?th row symbol unit of measure c degree celsius khz kilohertz k ? kilohm mhz megahertz m ? megaohm ? a microampere ? f microfarad ? s microsecond ma milliampere ms millisecond mv millivolt na nanoampere nf nanofarad ns nanosecond ? ohm pf picofarad ppm parts per million s second v volt w watt
document number: 001-67921 rev. *c revised october 31, 2012 page 28 of 28 all products and company names mentioned in this document may be the trademarks of their respective holders. cy8cmbr2016 ? cypress semiconductor corporation, 2011-2012. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions, and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution center s, manufacturer?s representatives, and distributors. to find t he office closest to you, visit us at cypress locations . products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/go/interface lighting & power control cypress.com/go/powerpsoc cypress.com/go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/image psoc cypress.com/go/psoc touch sensing cyp ress.com/go/touch usb controllers cypress.com/go/usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 document history page document title: cy8cmbr2016, capsense ? express? 16 button matrix controller document number: 001-67921 revision ecn orig. of change submission date description of change ** 3202566 msur 03/22/2011 new datasheet *a 3387102 msur 10/10/2011 changed status from preliminary to final. added char data into the table and some minor edits to the document. *b 3473096 msur 12/22/2011 no technical updates. *c 3633927 udyg 10/31/2012 updated title. updated features , scan rate , sensitivity , and button shorted to ground section. added parameters v il and v ih in ta b l e 11 , table 12 , and table 13 , and parameter t c in ta b l e 9 . added figure 15 and section response time . updated package information .

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